1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a writing and erasing method for the same.
Particularly, the present invention relates to a nonvolatile semiconductor memory device having a planarly dispersed charge storing means (for example, charge traps in a nitride film in a metal (generally, conductive gate)-oxide-nitride-oxide semiconductor (MONOS) element or metal (generally, conductive gate)-nitride-oxide semiconductor (MNOS) element), charge traps at a boundary region between an oxide film and the nitride film, small particle size semiconductors or conductors insulated from each other, etc.) in an internal portion of a gate insulating film between a channel forming region and gate electrode of a memory transistor which has as a basic operation to electrically inject a charge (electrons or holes) to the charge storing means to store or to extract charge from the charge storming means, and a writing and erasing method for the same.
More particularly, the present invention relates to application of a write inhibit voltage for effectively preventing erroneous writing or erroneous erasing in a non-selected memory transistor at the time of writing data to a selected memory transistor by supplying a predetermined bias voltage to each of a source, drain, and gate of the non-selected memory transistor.
2. Description of the Related Art
In today's sophisticated information society or high speed, wide area network society, there is a great need for large capacity file memories and audio-video use memories. At the present, as a large capacity memory system for storing more than 1 gigabyte (GB) of data, use is being made of disk memory systems using a disk such as a hard disk or optical disk as a recording medium. There has been lively research in recent years on replacing this big market by nonvolatile semiconductor memories.
While nonvolatile semiconductor memories dovetail with the trends of reduction of the size and reduction of the weight of the hardware, the storage capacity is still insufficient. A flash memory having over a 1 gigabit (Gb) capacity has not yet been realized. Further, nonvolatile semiconductor memories, in addition to the insufficient storage capacity, suffer from an insufficient reduction of the bit cost compared with a disk memory. Accordingly, it is important to increase the degree of integration of nonvolatile semiconductor memories to overcome these disadvantages.
There are generally the following two ways to raise the bit capacity of a nonvolatile semiconductor memory. The first method is to use a finer design rule in VLSI technology or an advanced circuitry of the memory cell or device structure to reduce the area occupied by the memory cell array and peripheral circuits. The second method is to make the memory transistors constituting the memory cells multi-valued so as to make a single transistor store a plurality of bits and thereby substantially raise the storage capacity with the same degree of integration. Both of the first and second methods are being studied in depth at the present time.
In the first method, miniaturization is being achieved by the so-called scaling rule. There are however various inherent problems in scaling to realize a more than 1 Gb large capacity semiconductor memory by a planarly contiguous floating gate (FG) type flash memory, particularly the difficulty of lowering of the operating voltage due to the fact that the thickness of the tunnel oxide film is not scaled (for example, see Nikkei Microdevices, January and February 1997). Namely, in an FG type flash memory, since the holding of the charge at the floating gate depends upon only the thickness of the tunnel oxide film, theoretical analysis of the back tunneling current from the floating gate shows that the thickness of the tunnel oxide film is physically limited to about 6 nm. However, a high electric field of about 10 MV/cm is used for writing the data in the current FG type flash memory at the stage before this physical limit is reached, therefore it has been pointed out that the stress leakage of the tunnel oxide film increases along with an increase of the number of rewrites of the data and that this stress leakage determines the effective limit of thickness of the tunnel oxide film. Due to the limit on the film thickness due to the increase of the stress leakage current, it is difficult to reduce the thickness of the tunnel oxide film to the 6 nm of the theoretical limit. It is thought that the realistic limit of thickness of the tunnel oxide film is 8 nm. For low voltage writing, the tunnel oxide film must be made thinner, but the limit of reduction of the thickness of the tunnel oxide film contradicts the scaling rule of lowering the voltage, therefore scaling of the write voltage has become difficult. As a result, the reduction of the area etc. of the peripheral circuits is becoming very difficult.
On the other hand, in the MONOS type nonvolatile memory, the carrier traps in the nitride film (Si.sub.x N.sub.y film; 0&lt;x&lt;1, 0&lt;y&lt;1) which mainly serves to hold the charge are discrete and spread out spatially (in the planar direction and thickness direction), therefore the data holding characteristic depends upon not only the thickness of the tunnel oxide film, but also the energy-wise and spatial distribution of the charges trapped by the carrier traps in the Si.sub.x N.sub.y film. When the charge storing means is made spatially discrete in this way, even when part of the tunnel oxide film is missing, it will have no great influence upon the retention (charge holding) characteristic of the overall memory element. For this reason, the problem of reduction of the thickness of the tunnel oxide film is not as serious as with the FG type, therefore the scaling property of the tunnel oxide film in a miniaturized ultra-fine memory transistor is better in the MONOS type than the FG type.
To reduce the bit cost and increase the density of integration for such a MONOS type or MNOS type nonvolatile memory and thereby realize a large scale nonvolatile memory, it is necessary to realize a one-transistor type cell structure. The conventional MONOS and other types of nonvolatile memories with thin tunnel oxide, however, have mainly been of the two-transistor type where a selection transistor is connected to the memory transistor. The establishment of a cell technique for realizing a one-transistor cell has been a key theme in the past. For establishment of this one-transistor cell technique, it is important not only to optimize the device structure, focusing on the gate insulating film containing the charge storing means, and improve the reliability, but also improve the disturb characteristic. However, there have been only a few reports on the read disturb characteristics of memory cells, in particular almost no reports on the programming disturb characteristic, since two-transistor cells have been studied up to now.